View IS61NSCS25672_557791.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IS61NSCS25672 IS61NSCS51236
RAM 256K x 72, 512K x 36
Features
* JEDEC SigmaRam pinout and package standard * Single 1.8V power supply (VCC): 1.7V (min) to 1.9V (max) * Dedicated output supply voltage (VCCQ): 1.8V or 1.5V typical * LVCMOS-compatible I/O interface * Common data I/O pins (DQs) * Single Data Rate (SDR) data transfers * Pipelined (PL) read operations * Double Late Write (DLW) write operations * Burst and non-burst read and write operations, selectable via dedicated control pin (ADV) * Internally controlled Linear Burst address sequencing during burst operations * Burst length of 2, 3, or 4, with automatic address wrap * Full read/write coherency * Byte write capability * Two cycle deselect * Single-ended input clock (CLK) * Data-referenced output clocks (CQ/CQ) * Selectable output driver impedance via dedicated control pin (ZQ) * Echo clock outputs track data output drivers * Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3) * JTAG boundary scan (subset of IEEE standard 1149.1) * 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
ISSI
(R)
ADVANCE INFORMATION JUNE 2001
18Mb Synchronous SRAM
Bottom View
209-Bump, 14 mm x 22 mm BGA 1 mm Bump Pitch, 11 x 19 Bump Array
SigmaRAM Family Overview
The IS61NSCS series RAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. The implementations are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage CMOS I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. ISSI' RAMs are offered in a number of configurations that s emulate other synchronous SRAMs, such as Burst RAMs, NBT RAMs, Late Write, or Double Data Rate (DDR) SRAMs. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering and write cueing. RAMs allow a user to implement the interface protocol best suited to the task at hand. This specific product is Common I/O, SDR, Double Late Write & Pipelined Read (same as Pipelined NBT) and in the family is identified as 1x1Dp.
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
1
IS61NSCS25672 IS61NSCS51236
Functional Description
Because SigmaRAM is a synchronous device, address, data Inputs, and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.
ISSI
(R)
Single data rate RAMs incorporate a rising-edge-triggered output register. For read cycles, RAM's output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. IS61NSCS series RAMs are implemented with ISSI's high performance CMOS technology and are packaged in a 209-bump BGA.
IS61NSCS25672 PINOUT 256K x 72 Common I/O--Top View
1 A B C D E F G H J K L M N P R T U V W DQg DQg DQg DQg DQPg DQc DQc DQc DQc CQ2 DQh DQh DQh DQh DQPd DQd DQd DQd DQd 2 DQg DQg DQg DQg DQPc DQc DQc DQc DQc CQ2 DQh DQh DQh DQh DQPh DQd DQd DQd DQd 3 A Bc Bh GND VCCQ GND VCCQ GND VCCQ CLK VCCQ GND VCCQ GND VCCQ GND NC A TMS 4 E2 Bg Bd NC VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ NC A A TDI 5 A (16M) NC NC (128M) NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC NC (64M) A A 6 ADV W E1 MCL VCC ZQ EP2 EP3 M4 MCL M2 M3 SD MCL VCC MCL A A1 A0 7 A (8M) A NC NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC NC (32M) A A 8 E3 Bb Be NC VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ NC A A TDO 9 A Bf Ba GND VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ GND NC A TCK 10 DQb DQb DQb DQb DQPf DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQPa DQe DQe DQe DQe 11 DQb DQb DQb DQb DQPb DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQPe DQe DQe DQe DQe
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
IS61NSCS51236 PINOUT 512K x 36 Common I/O--Top View
1 A B C D E F G H J K L M N P R T U V W NC NC NC NC NC DQc DQc DQc DQc CQ2 NC NC NC NC DQPd DQd DQd DQd DQd 2 NC NC NC NC DQPc DQc DQc DQc DQc CQ2 NC NC NC NC NC DQd DQd DQd DQd 3 A Bc NC GND VCCQ GND VCCQ GND VCCQ CLK VCCQ GND VCCQ GND VCCQ GND NC A TMS 4 E2 NC Bd NC VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ NC A A TDI 5 A (16M) A (x36) NC (128M) NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC NC (64M) A A 6 ADV W E1 MCL VCC ZQ EP2 EP3 M4 MCL M2 M3 SD MCL VCC MCL A A1 A0 7 A A NC NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC NC (32M) A A 8 E3 Bb NC NC VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ NC A A TDO 9 A NC Ba GND VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ GND NC A TCK
ISSI
10 DQb DQb DQb DQb NC NC NC NC NC CQ1 DQa DQa DQa DQa DQPa NC NC NC NC 11 DQb DQb DQb DQb DQPb NC NC NC NC CQ1 DQa DQa DQa DQa NC NC NC NC NC
(R)
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
3
IS61NSCS25672 IS61NSCS51236
PIN DESCRIPTION TABLE
Symbol A Pin Location A3, A5, A7, A9, B7, U4, U6, U8, V3, V4, V5, V6, V7, V8, V9, W5, W6, W7 B5 A6 B3, C9 B8, C4 B4, B9, C3, C8 K3 K1, K11 K2, K10 E2, F1, F2, G1, G2, H1, H2, J1, J2, L10, L11, M10, M11, N10, N11, P10, P11, R10 A10, A11, B10, B11, C10, C11, D10, D11, E11, R1, T1, T2, U1, U2, V1, V2, W1, W2 A1, A2, B1, B2, C1, C2, D1, D2, E1, E10, F10, F11, G10, G11, H10, H11, J10, J11, L1, L2, M1, M2, N1, N2, P1, P2, R2, R11, T10, T11, U10, U11, V10, V11, W10, W11 C6 A4, A8 G6, H6 W9 W4 W8 W3 L6, M6, J6 N6 B3, C9, D6, K6 P6, T6, W6 Description Address Type Input
ISSI
Comments --
(R)
A ADV Bx Bx Bx CK CQ CQ DQ
Address Advance Byte Write Enable Byte Write Enable Byte Write Enable Clock Echo Clock Echo Clock Data I/O
Input Input Input Input Input Input Output Output Input/Output
x36 version Active High Active Low (all versions) Active Low (x36 and x72 versions) Active Low (x72 version only) Active High Active High Active Low x36, and x72 versions
Data I/O
Input/Output
DQ
Data I/O
Input/Output
x72 version only
E1 E2 & E3 EP2 & EP3 TCK TDI TDO TMS M2, M3 & M4 SD MCL
Chip Enable Chip Enable Chip Enable Program Pin Test Clock Test Data In Test Data Out Test Mode Select Mode Control Pins Slow Down Must Connect Low
Input Input Input Input Input Output Input Input Input Input
Active Low Programmable Active High or Low -- Active High -- -- -- -- Active Low --
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
PIN DESCRIPTION TABLE
Symbol NC NC NC Pin Location C5, D4, D5, D7, D8, K4, K8, K9, T4, T5, T7, T8, U3, U5, U7, U9 B5 C7 A1, A2, B1, B2, B4, B9, C1, C2, C3, C8, D1, D2, E1, E10, F10, F11, G10, G11, H10, H11, J10, J11, L1, L2, M1, M2, N1, N2, P1, P2, R2, R11, T10, T11, U10, U11, V10, V11, W10, W11 B6 E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5, R6, R7 Description No Connect No Connect No Connect Type -- -- --
ISSI
Comments
(R)
Not connected to die (all versions) Not connected to die (x72 version) Not connected to die (x72/x36 versions)
NC
No Connect
--
Not connected to die (x36 version)
W VCC
Write Core Power Supply
Input Input
Active Low 1.8 V Nominal
VCCQ
E3, E4, E8, E9, J3, J4, J8, J9, L3, L4, L8, Output Driver Power Supply L9, N3, N4, N8, N9, R3, R4, R8, R9 D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7, H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3, P4, P5, P7, P8, P9, T3, T9 F6
Input
1.8 V or 1.5 V Nominal
GND
Ground
Input
--
ZQ
Output Impedance Control
Input
Low = Low Impedance [High Drive] High = High Impedance [Low Drive] Default = High
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
5
IS61NSCS25672 IS61NSCS51236
BACKGROUND
The central characteristics of the ISSI RAMs are that they are extremely fast and consume very little power. Because both operating and interface power is low, RAMs can be implemented in a wide (x72) configuration, providing very high single package bandwidth (in excess of 20 Gb/s in ordinary pipelined configuration) and very low random access latency (5 ns). The use of very low voltage circuits in the core and 1.8V or 1.5V interface voltages allow the speed, power and density performance of RAMs. Although the SigmaRAM family pinouts have been designed to support a number of different common read and write protocol options, not all SigmaRAM implementations will support all possible protocols. The following timing diagrams provide a quick comparison between read and write protocols options available in the context of the SigmaRAM
ISSI
(R)
standard. This data sheet covers the single data rate (nonDDR), Double Late Write, Pipelined Read SigmaRAM. The character of the applications for fast synchronous SRAMs in networking systems are extremely diverse. RAMs have been developed to address the diverse needs of the networking market in a manner that can be supported with a unified development and manufacturing infrastructure. RAMs address each of the bus protocol options commonly found in networking systems. This allows the RAM to find application in radical shrinks and speed-ups of existing networking chip sets that were designed for use with older SRAMs, like the NBT or Nt, Late Write, or Double Data Rate SRAMs, as well as with new chip sets and ASIC's that employ the Echo Clocks and realize the full potential of the RAMs.
COMMON I/O SigmaRAM FAMILY MODE COMPARISON--LATE WRITE VS. DOUBLE LATE WRITE Double Late Write--Pipelined Read (1x1Dp). For reference only.
CK Address Control DQ CQ A R B W QA C R D W DB QC E R F W DD QE
Late Write--Pipelined Read (1x1Lp). For reference only.
CK Address Control DQ CQ A R B X QA C W D R DC E X QD F W DF
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
Double Data Rate Write--Double Data Rate Read (1x2Lp). For reference only.
CK Address Control DQ CQ A R B X QA0 C W QA1 D R
DC0 DC1
ISSI
E X QD0 F W QD1
DF0
(R)
Mode Selection Truth Table Standard
Name 1x2Lp 1x1Dp 1x1Lp M2 0 1 1 M3 1 0 1 M4 1 1 0 Function DDR Double Late Write, Pipelined Read Late Write, Pipelined Read Analogous to... Double Data Rate SRAM Pipelined NBT SRAM Pipelined Late Write SRAM In This Data Sheet? No Yes No
Notes: All address, data and control inputs (with the exception of EP2, EP3, and the mode pins, M2-M4) are synchronized to rising clock edges. Read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1-CQn.
READ OPERATIONS Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
WRITE OPERATIONS
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active and the write enable input signal (W) is asserted low.
Double Late Write
Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement Pipeline mode NBT SRAMs.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
7
IS61NSCS25672 IS61NSCS51236
Single Data Rate Pipelined Read
ISSI
(R)
CLK
Address
A
XX
C
D
E
F
E1
W
DQ
QA
QC
QD
CQ
Read
Deselect
Read
Read
Read
Double Late Write with Pipelined Read
CLK
Address
A
B
C
D
E
F
E1
W
DQ
QA
DB
QC
DD
CQ
Read
Write
Read
Write
Read
Write
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
SPECIAL FUNCTIONS Slow Down Mode
The SD pin allows the user to activate a delay element in the on-chip clock chain that is routed to the data and echo Clock output drivers. Activating Slow Down mode by pulling the SD pin low introduces extra delay in every synchronous output driver specification. Address, control and data input specifications are not affected by Slow Down Mode. See "Slow Down Mode Clock to Data Out and Clock to Echo Clock Timing" table for specifics.
ISSI
Burst Order
(R)
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. SigmaRAMs always count in linear burst order.
Linear Burst Order
A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 A[1:0] 01 10 11 00 A[1:0] 10 11 00 01 A[1:0] 11 00 01 10
Burst Cycles
RAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the RAM to advance the internal address counter and use the counter generated address to read or write the RAM. The starting address for the first cycle in a burst cycle series is loaded into the RAM by driving the ADV pin low, into Load mode.
Note: 1. The burst counter wraps to initial state on the 5th rising edge of clock.
Sigma Pipelined Burst Reads with Counter Wrap-around
CLK
External Address
A2
XX
XX
XX
XX
XX
Internal Address
A2
A3
A0
A1
A2
A3 Counter Wraps
E1
W
ADV DQ QA2 QA3 QA0 QA1
CQ Read Continue Continue Continue Continue
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
9
IS61NSCS25672 IS61NSCS51236
Echo Clock
RAMs feature Echo Clocks, CQ1,CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are delayed copies of the main RAM clock, CLK. Echo Clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. Sigma RAMs provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2). It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of Echo Clock drivers is always pipelined to
ISSI
(R)
the same degree as output data. Deselection of the RAM via E1 does not deactivate the Echo Clocks. In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming read operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2 would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.
Echo Clock Control in Two Banks of Sigma Pipelined SRAMs
CLK
Address
A
B
C
D
E
F
E1
E2 Bank 1 E2 Bank 2
DQ Bank 1
QA
QC
DQ Bank 2
QB
QD
CQ Bank 1
CQ Bank 2
CQ1+ CQ2
Read
Read
Read
Read
Read
Read
Note: E1 does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
Echo Clock Continued:
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the Echo Clocks. In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming read operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank.
ISSI
(R)
Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2 would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.
Pipelined Read Bank Switch with E1 Deselect
CLK
Address
A
XX
C
D
E
F
E1
E2 Bank 1 E2 Bank 2
DQ Bank 1
QA
DQ Bank 2
QC
QD
CQ Bank 1
CQ Bank 2
CQ1+ CQ2
Read
No Op
Read
Read
Read
Read
Note: E1 does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
11
IS61NSCS25672 IS61NSCS51236
ISSI
(R)
Output Driver Impedance Control
SigmaRAMs may be supplied with either selectable (high) impedance output drivers. The ZQ pin of SigmaRAMs supplied with selectable impedance drivers, allows selection between RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications. The impedance of the data and clock output drivers in these devices can be controlled via the static input ZQ. When ZQ is tied "low", output driver impedance is set to ~25 . When ZQ is tied "high" or left unconnected, output driver impedeance is set to ~50. See the DC Electrical Characteristics section for further information. The SRAM requires 32K cycles of power-up time after VCC reaches its operating range.
Output Driver Characteristics - TBD
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
Programmable Enables
SRAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at VCC , E2 functions as an active high enable. If EP2 is held to GND , E2 functions as an active low chip enable input.
ISSI
(R)
Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming the enable inputs of four SRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four SRAMs can be made to look like one larger RAM to the system.
BANK ENABLE TRUTH TABLE
EP2 Bank 0 Bank 1 Bank 2 Bank 3 GND GND Vcc Vcc EP3 GND Vcc GND Vcc E2 Active Low Active Low Active High Active High E3 Active Low Active High Active Low Active High
EXAMPLE FOUR BANK DEPTH EXPANSION SCHEMATIC
A0-An E1 CLK W DQ0-DQn Bank 0 A0-An-2 A An-1 E3 An E2 E1 CLK W DQ CQ CQ Bank 1 A0-An-2 A An-1 E3 An E2 E1 CLK W DQ CQ Bank 2 A0-An-2 A An-1 E3 An E2 E1 CLK W DQ CQ Bank 3 A0-An-2 A An-1 E3 An E2 E1 CLK W DQ CQ
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
13
IS61NSCS25672 IS61NSCS51236
SYNCHRONOUS TRUTH TABLE
CLK 01 01 01 01 01 E1 (tn) X X 1 X 0 E ADV W BW (tn) (tn) (tn) (tn) F X T X T 0 1 0 1 0 X X X X 0 X X X X T Previous Operation X Bank Deselect X Deselect X Current Operation Bank Deselect Bank Deselect (Continue) Deselect Deselect (Continue) Write Loads new address Stores DQx if BWx = 0 Write (Abort) Loads new address No data stored Write Continue Increments address by 1 Stores DQx if BWx = 0 Write Continue (Abort) Increments address by 1 No data stored Read Loads new address Read Continue Increments address by 1 DQ/CQ (tn) *** Hi-Z *** Hi-Z/CQ ***
ISSI
DQ/CQ (tn+1) Hi-Z Hi-Z Hi-Z/CQ Hi-Z/CQ Dn/CQ (tn) Hi-Z/CQ
(R)
01
0
T
0
0
F
X
***
01
X
X
1
X
T
Write
Dn-1/CQ (tn-1) Dn-1/CQ (tn-1) *** Qn-1/CQ (tn-1)
Dn/CQ (tn) Hi-Z/CQ
01
X
X
1
X
F
Write
01 01
0 X
T X
0 1
1 X
X X
X Read
Qn/CQ (tn) Qn/CQ (tn)
Notes: 1. If E2 = EP2 and E3 = EP3 then E = "T" else E = "F". 2. If one or more BWx = 0 then BW = "T" else BW = "F". 3. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false". 4. "***" indicates that the DQ input requirement/output state and CQ output state are determined by the previous operation. 5. DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled. 6. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled. 7. Up to 3 Continue operations may be initiated after iniating a Read or Write operation to burst transfer up to 4 distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address.
14
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
READ/WRITE CONTROL STATE DIAGRAM
ISSI
0,T,0,0
(R)
0,T,0,1 0,T,0,1 READ X,F,0,X X,F,0,X X,X,1,X BANK DESELECT 0,T,0,1 1,T,0,X READ CONTINUE X,F,0,X 0,T,0,1 1,T,0,X 1,T,0,X or X,X,1,X DESELECT X,F,0,X X,X,1,X 1,T,0,X 0,T,0,0 X,F,0,X WRITE CONTINUE 0,T,0,0 1,T,0,X 0,T,0,0 WRITE
1,T,0,X X,X,1,X
0,T,0,1
0,T,0,0
X,F,0,X or X,X,1,X
0,T,0,0 X,X,1,X
0,T,0,1
Notes: 1. The notation "X,X,X,X" controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively. 2. If (E2 = EP2 and E3 = EP3) then E = "T" else E = "F". 3. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false".
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
15
IS61NSCS25672 IS61NSCS51236
Current State & Next State Definition for Read/Write Control State Diagram
n n+1 n+2 n+3
ISSI
CK
(R)
Command
Current State
Next State
KEY
Input Command Code Transition
Current State (n)
Next State (n+1)
ABSOLUTE MAXIMUM RATINGS
(All voltages reference to GND ) Symbol VCC VCCQ VI/O VIN IIN IOUT TJ TSTG Description Voltage on VCC Pins Voltage in VCCQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any Pin Maximum Junction Temperature Storage Temperature Value -0.5 to 2.5 -0.5 to 2.3V -0.5 to VCCQ +0.5 ( 2.3 V max.) -0.5 to VCCQ +0.5 ( 2.3 V max.) 100 100 125 -55 to 125 Unit V V V V mA dc mA dc C C
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Operation should be limited to Recommended Operating Conditions. Exposure to conditions exceeding Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.
POWER SUPPLY CHARACTERISTICS (TA = 0 min., 25 typ, 70 max C)
Symbol VCC VCCQ(1) Parameter Supply Voltage 1.8 V I/O Supply Voltage 1.5 V I/O Supply Voltage Min. 1.7 1.7 1.4 Typ. 1.8 1.8 1.5 Max. 1.9 VCC 1.6 V Unit V V V
Note: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V VCCQ 1.6V (i.e., 1.5 V I/O) and 1.7 V VCCQ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.
16
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
CMOS I/O DC Input Characteristics
Symbol VIH VIL Parameter CMOS Input High Voltage CMOS Input Low Voltage VCCQ 1.8 1.5 1.8 1.5 Min. 1.2 1.0 -0.3 -0.3 Typ. -- -- -- --
ISSI
Max. VCCQ + 0.3 VCCQ + 0.3 0.6 0.5 Unit V V
(R)
Note: For devices supplied with CMOS input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH VCC + 1.0V GND 50% GND - 1.0V 20% tKC VIL 50% VCC
20% tKC
I/O CAPACITANCE (TA = 25 C, f = 1 MHZ)
Symbol CA CB CCK CDQ CCQ Parameter Address Control Clock Data CQ Clock Input Capacitance Input Capacitance Input Capacitance Output Capacitance Output Capacitance Test conditions VIN = 0 V VIN = 0 V VIN = 0 V VOUT = 0 V VOUT = 0 V Min. -- -- -- -- -- Max. 3.5 3.5 3.5 4.5 4.5 Unit pF pF pF pF pF
Note: These parameters are sampled and not 100% tested.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
17
IS61NSCS25672 IS61NSCS51236
AC TEST CONDITIONS
(VCC = 1.8V 0.1V, TA = 0 to 85C) Parameter VCCQ Input High Level Input Low Level Input Rise & Fall Time Input Reference Level Clock Input High Voltage Clock Input Low Voltage Clock Input Rise & Fall Time Clock Input Reference Level Output Reference Level Output Load Conditions ZQ = VIH VKIH VKIL VIH VIL Symbol 1.25 0.25 2.0 0.75 1.25 0.25 2.0 0.75 0.75 see below Conditions 1.5V0.1 1.8 0.1 1.4 0.4 2.0 0.9 1.4 0.4 2.0 0.9 0.9 see below
ISSI
Units V V V V/ns V V V V/ns V V
(R)
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown unless otherwise noted.
AC TEST LOADS
VCCQ = 1.5V 16.7 16.7 DQ 16.7 50 50
0.75V 50
VCCQ = 1.8V 16.7 5 pF 16.7 DQ 16.7 50 50
0.9V 50 5 pF
5 pF 50 0.75V
5 pF 50 0.9V
Figure 1 (VCCQ = 1.5V)
Figure 2 (VCCQ = 1.8V)
18
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
INPUT AND OUTPUT LEAKAGE CHARACTERISTICS
Symbol IIL IINM IOL Parameter Input Leakage Current (except mode pins) Mode Pin Input Current Output Leakage Current Test Conditions VIN = 0 to VCC VCC VIN VIL 0V VIN VIL Output Disable, VOUT = 0 to VCCQ Min. -2 -100 -2 -2 Max. 2 2 2 2 Units A A A
ISSI
(R)
SELECTABLE IMPEDANCE OUTPUT DRIVER DC ELECTRICAL CHARACTERISTICS
Symbol VOHL(1) VOLL
(1) (2)
Parameter Low Drive Output High Voltage Low Drive Output Low Voltage High Drive Output High Voltage High Drive Output Low Voltage
Test Conditions IOHL = -4 mA IOLL = 4 mA IOHH = -8 mA IOLH = 8 mA
Min. VCCQ - 0.4 -- VCCQ - 0.4 --
Max. -- 0.4 -- 0.4
Units V V V V
VOHH VOLH
(2)
Notes: 1. ZQ = 1; High Impedance output driver setting 2. ZQ = 0; Low Impedance output driver setting
OUTPUT RESISTANCE
Symbol ROUT Parameter Output Resistance Test Conditions VOH, VOL = VCCQ/2 ZQ = VIL VOH, VOL = VCCQ/2 ZQ = VIH Min. 17 35 Typ. 25 50 Max. 33 65 Units
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
19
IS61NSCS25672 IS61NSCS51236
ISSI
Test Conditions Pipeline x72 x36 Flow-through x72 x36 Pipeline x72 x36 Flow-through x72 x36 -333 Com. Ind. -300 Com. Ind. -250 Com. Ind.
(R)
OPERATING CURRENTS
Symbol ICCP Parameter Pipeline Operating Current Units mA
ICCF ISB1 & ISB2
E1 < VIL Max. tKHKH > tKHKH Min. All other inputs Flow-through Operating Current VIL = VIN > VIH Bank Deselect Current & Chip Disable Current E1 < VIH Min. or E2 or E3 False tKHKH > tKHKH Min. All other inputs VIL > VIN > VIH
mA
IDD3
CMOS Deselect Current
Device Deselected Pipeline x72 All inputs x36 GND+0.10V > VIN > VCC-0.10V Flow-through x72 x36 IOUT = 0mA VIN = VIH or VIL Pipeline x72 x36 Flow-through x72 x36 Pipeline x72 x36 Flow-through x72 x36 750 550
mA
ICC
Average Power Supply Operating Current
mA
ICC2
Power Supply Deselect Operating Current
IOUT = 0mA VIN = VIH or VIL
250
mA
Note: Com. = 0C to 70C Ind. = -40C to +85C
DC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V 0.1V, GND = 0V, TA = 0 to 85C) Symbol ILI IMLI IDLI Parameter Input Leakage Current (Address, Control, Clock) Input Leakage Current (EP2, EP3, M2, M3, M4, ZQ) Input Leakage Current (Data) Test Conditions VIN = GND to VCCQ VMIN = GND to VCC VDIN = GND to VCCQ Min -5 -10 -10 Typ -- -- -- Max 5 10 10 Units uA uA uA
20
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
AC ELECTRICAL CHARACTERISTICS
Symbol tKHKH tKHKL tKLKH tKHCX1
(2)
ISSI
-333 Min Max 3.0 1.2 1.2 0.5 0.5 0.5 -- 0.5 -- 0.5 0.5 -- -- 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 -- -- -- -- 1.5 1.5 1.5 -- 1.6 -- 1.6 0.4 -0.4 -- -- -- -- -- -- -- -- -- -- -- -- -300 Min Max 3.3 1.3 1.3 0.5 0.5 0.5 -- 0.5 -- 0.5 0.5 -- -- 0.7 0.4 0.7 0.4 0.7 0.4 0.7 0.4 0.7 0.4 0.7 0.4 -- -- -- -- 1.7 1.7 1.7 -- 1.8 -- 1.8 0.4 -0.4 -- -- -- -- -- -- -- -- -- -- -- -- -250 Min Max 4.0 1.5 1.5 0.5 0.5 0.5 -- 0.5 -- 0.5 0.5 -- -- 0.8 0.5 0.8 0.5 0.8 0.5 0.8 0.5 0.8 0.5 0.8 0.5 -- -- -- -- 2.0 2.0 2.0 -- 2.1 -- 2.1 0.5 -0.5 -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(R)
Parameter Clock Cycle Time Clock HIGH Time Clock LOW Time Clock High to Echo Clock Low-Z Clock High to Echo Clock High Echo Clock High Time Clock Low to Echo Clock Low Echo Clock Low Time Clock High to Echo Clock High-Z Clock High to Output in Low-Z Clock High to Output Valid Clock High to Output Invalid Clock High to Output in High-Z Echo Clock High to Output Valid Output Invalid to Echo Clock High Address Valid to Clock High Clock High to Address Don't Care Enable Valid to Clock High Clock High to Enable Don't Care Write Valid to Clock High Clock High to Write Don't Care Byte Write Valid to Clock High Clock High to Byte Write Don't Care Data In Valid to Clock High Clock High to Data In Don't Care ADV Valid to Clock High Clock High to ADV Don't Care
tKHCH tCHCL(2) tKLCL tCLCH
(2) 2)
tKHKL 200 ps tKLKH 200 ps
tKHKL 200 ps tKLKH 200 ps
tKHKL 250 ps tKLKH 250 ps
tKHCZ(1, tKHQX1 tKHQV tKHQX
(1)
tKHQZ(1) tCHQV tCHQX
(2) (2)
tAVKH tKHAX tEVKH tKHEX tWVKH tKHWX tBVKH tKHBX tDVKH tKHDX tadvVKH tKHadvX
Notes: 1. Measured at 100 mV from steady state. Not 100% tested. 2. Guaranteed by design. Not 100% tested. 3. For any specific temperature and voltage tKHCZ < tKHCX1.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
21
IS61NSCS25672 IS61NSCS51236
ISSI
-333 Min Max 1.1 1.1 -- 2.4 -300 Min Max 1.1 1.1 -- 2.6 -250 Min Max 1.1 1.1 -- 3.1 ns ns ns ns ns ns ns ns ns ns ns
(R)
SLOW DONW MODE CLOCK TO DATA OUT and CLOCK TO ECHO CLOCK TIMING
Symbol tKHCX1(2) tKHCH tCHCL tCLCH
(2) (2) 2)
Parameter Clock High to Echo Clock Low-Z Clock High to Echo Clock High Echo Clock High Time Echo Clock Low Time Clock High to Echo Clock High-Z Clock High to Output in Low-Z Clock High to Output Valid Clock High to Output Invalid Clock High to Output in High-Z Echo Clock High to Output Valid Echo Clock High to Output Invalid
Unit
tKHKL 300 ps tKLKH 300 ps
tKHKL 300 ps tKLKH 300 ps
tKHKL 350 ps tKLKH 350 ps 1.1 1.1 -- 1.1 1.1 -- -- 3.1 -- 3.2 -- 3.2 0.6 -0.6
tKHCZ(1, tKHQV tKHQX
1.1 1.1 -- 1.1 1.1 -- --
2.4 -- 2.5 -- 2.5 0.5 -0.5
1.1 1.1 -- 1.1 1.1 -- --
2.6 -- 2.7 -- 2.7 0.5 -0.5
tKHQX1(1)
tKHQZ(1) tCHQV tCHQX
(2) (2)
Notes: 1. Measured at 100 mV from steady state. Not 100% tested. 2. Guaranteed by design. Not 100% tested. 3. For any specific temperature and voltage tKHCZ < tKHCX1.
22
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
TIMING PARAMETER KEY--PIPELINED READ CYCLE TIMING
tKHKH CK tKHAX tAVKH C D tKHQZ tKHQX DQ (DDR) tKHQV tKHQX1 QB E tKLKH tKHKL
ISSI
(R)
tCHQV tKHCH tKHCX1 tCHCL tCLCH
tCHQX
tKHCZ
CQ
= CQ High Z
TIMING PARAMETER KEY--DOUBLE LATE WRITE MODE CONTROL AND DATA IN TIMING
CK tKHAX tAVKH A A tnVKH E1, E2, E3 W, Bn, ADV tDVKH DQ DA tKHDX B C
tKHnX
Note: tnVKH = tEVKH, tWVKH, tBVKH, etc. and tKHnX = tKHEX, tKHWX, tKHBX, etc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
23
IS61NSCS25672 IS61NSCS51236
ISSI
(R)
JTAG PORT OPERATION Overview
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1 functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP Controller and four TAP Registers. The TAP Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers).
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. To assure normal operation of the RAM with the JTAG Port unused, TCK should be tied Low, TDI and TMS may be left floating or tied to VCC . TDO should be left unconnected.
JTAG PIN DESCRIPTIONS Pin
TCK TMS
Pin Name
Test Clock Test Mode Select
I/O
In In
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. Output that is active depending on the state of the TAP Controller. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
TDI
Test Data In
In
TDO
Test Data Out
Out
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
24
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
JTAG PORT REGISTERS Overview
The JTAG registers, refered to as Test Access Port (TAP) registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.
ISSI
Bypass Register
(R)
The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the following Scan Order Table. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.
JTAG TAP Block Diagram
0 Bypass Register TDI 210 Instruction Register 31 30 29 ID Code Register TDO 210
n 210 Boundary Scan Register TMS TCK
. .. ... ..
Test Access Port (TAP) Controller
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
25
IS61NSCS25672 IS61NSCS51236
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from
ISSI
(R)
a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die Revision Code Bit # x72 x36 I/O Configuration ISSI Technology JEDEC Vendor ID Code
Presence Register
Not Used
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 XXXX00000000000011 0000011010101 XXXX00 00 00 000 00 010 00 0001 1 010 10 1
0 1 1
JTAG TAP CONTROLLER STATE DIAGRAM
Test Logic Reset 1 0 Run Test Idle 0 1 1 Select DR 0 Capture DR 0 Shift DR 1 1 Exit1 DR 0 Pause DR 0 1 Exit2 DR 1 1 Update DR 0 0 1 Select IR 0 1 Capture IR 0 Shift IR 1 1 Exit1 IR 0 Pause IR 1 Exit2 IR 1 1
0
0
0 0
1
Update IR 0
26
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
ISSI
(R)
TAP CONTROLLER INSTRUCTION SET Overview
There are two classes of instructions defined in the Standard 1149.1-1990; standard (public) instructions, and device specific (private) instructions. Some public instructions are mandatory for 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads.This device will not perform INTEST but can preform the preload portion of the SAMPLE/PRELOAD command.
When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state, the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the JTAG TAP Instruction Set Summary.
JTAG TAP Instruction Set Summary
Instruction EXTEST
(1)
Code 000 001 010 011 100 101 110
Description Places the Boundary Scan Register between TDI and TDO. When EXTEST is selected, data will be driven out of the DQ pad. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all Data and Clock output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Private instruction. Do not use this instruction; Reserved for Future Use. Places Bypass Register between TDI and TDO.
IDCODE(1,2) SAMPLE-Z(1) RFU(1) SAMPLE/PRELOAD(1) Private RFU(1) BYPASS
(1) (1)
111
Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in Test-Logic-Reset state.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
27
IS61NSCS25672 IS61NSCS51236
ISSI
(R)
JTAG DC RECOMMENDED OPERATING CONDITIONS (TA = 0 to 85C)
Symbol VTIH VTIL VTOH VTOL ITLI Parameter JTAG Input High Voltage JTAG Input Low Voltage JTAG Output High Voltage JTAG Output Low Voltage JTAG Input Leakage Current CMOS TTL CMOS TTL ITOH = -100 ITOH = -8m ITOL = 100 ITOL = 8m VTIN=GND to VCC Test Conditions Min. 1.2 -0.3 VCC-0.1 VCC-0.4 -- -- -10 Max. VCC +0.3 0.6 -- -- 0.1 0.4 10 Unit V V V V
JTAG AC TEST CONDITIONS (VCC = 1.8V 0.1V, TA = 0 to 85C)
Symbol VTIH VTIL Parameter JTAG Input High Voltage JTAG Input Low Voltage JTAG Input Rise & Fall Time JTAG Input Reference Level JTAG Output Reference Level JTAG Output Load Condition Test Conditions 1.6 0.2 1.0 0.9 0.9 Unit V V V/ns V V
see AC TEST LOADS
28
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
ISSI
Min 20 8 8 5 5 5 5 -- 0 Max -- -- -- -- -- -- -- 10 -- Unit ns ns ns ns ns ns ns ns ns
(R)
JTAG Port AC Electrical Characteristics
Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tTLQV tTLQX Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Setup Time TMS Hold Time TDI Set Up Time TDI Hold Time TCK Low to TDO Valid TCK Low to TDO Hold
JTAG Port Timing Diagram
tTHTL TCK
tTLTH
tTHTH
tMVTH tTHMX TMS tDVTH tTHDX TDI
TDO tTLQX tTLQV
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
29
IS61NSCS25672 IS61NSCS51236
ISSI
(R)
INSTRUCTION DESCRIPTIONS BYPASS
When the BYPASS instruction is loaded to the Instruction Register, the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the state of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin (pin marked NC), are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Some Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the BSDL file. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAP's input data capture set-up plus hold time (tTS plus tTH ). The RAM's clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the Boundary Scan Register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded to the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded to the instruction register, all RAM outputs are forced to inactive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
EXTEST (EXTEST-A)
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output
RFU
These instructions are reserved for future use. In this device they replicate the BYPASS instruction.
30
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01
IS61NSCS25672 IS61NSCS51236
Boundary Scan Order Assignments (by Exit Sequence) -TBD
ISSI
(R)
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 06/19/01 Rev. 00A
31
IS61NSCS25672 IS61NSCS51236
ORDERING INFORMATION Commercial Range: 0C to 70C
Frequency 256K x 72 250 300 333 512K x 36 250 300 333 Order Part No. IS61NSCS25672-250B IS61NSCS25672-300B IS61NSCS25672-333B IS61NSCS51236-250B IS61NSCS51236-300B IS61NSCS51236-333B Package
ISSI
209-pin BGA 209-pin BGA 209-pin BGA 209-pin BGA 209-pin BGA 209-pin BGA
(R)
Industrial Range: -40C to 85C
FrequencySpeed (ns) Order Part No. Package
TBD
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
32
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00A 06/19/01

▲Up To Search▲

Price & Availability of IS61NSCS25672

	To Download IS61NSCS25672 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .